1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device (semiconductor integrated circuit apparatus) in which a signal input portion has an amplifying circuit including one or two or more insulating gate type transistors such as MOS transistors and which can process, especially, a micro signal.
2. Related Background Art
As one of constructional examples of a simple amplifying circuit, an inverter circuit using an MOS transistor of a complementary type (hereinbelow, referred to as a CMOS) constructed as shown in a schematic circuit diagram of FIG. 1 is considered. That is, in FIG. 1, a source of a P-channel MOS transistor (hereinbelow, referred to as a PMOS Tr) M1 is connected to a V.sub.DD power source terminal 100, a drain of the PMOS Tr M1 is commonly connected to a drain of an N-channel MOS transistor (hereinbelow, referred to as an NMOS Tr) M2, a source of the NMOS Tr M2 is connected to a ground terminal 101, gates of the PMOS Tr M1 and NMOS Tr M2 are commonly connected to an input terminal 1, a back gate of the PMOS Tr M1 is connected to the V.sub.DD power source terminal 100, and a back gate of the NMOS Tr M2 is connected to the ground terminal 101, thereby constructing a CMOS inverter. An output of the CMOS inverter constructed by the PMOS Tr M1 and NMOS Tr M2 is connected to an input of an internal circuit (a CMOS inverter constructed by a PMOS Tr M3 and an NMOS Tr M4 in a manner similar to the CMOS inverter constructed by the PMOS Tr M1 and NMOS Tr M2 in FIG. 1). In this case, the PMOS Tr M1 of the input inverter and the PMOS Tr M3 of the internal circuit are formed on a same N well 12 as shown in FIG. 2 and the NMOS Tr M2 of the input inverter and the NMOS Tr M4 of the internal circuit are formed on a P-type substrate 15.
In FIG. 2, reference numeral 2001 denotes an n.sup.- region formed in the P-type substrate 15. The PMOS Trs M1 and M3 are formed in this n.sup.- region. Reference numerals 2002, 2003, 2004, and 2005 indicate p.sup.+ regions formed in the n.sup.- region 2001, respectively. In FIG. 2, the p.sup.+ region 2003 becomes a source region of the PMOS Tr M1, the p.sup.+ region 2005 becomes a source region of the PMOS Tr M3, the p.sup.+ region 2002 becomes a drain region of the PMOS Tr M1, and the p.sup.+ region 2004 becomes a drain region of the PMOS Tr M3. Reference numerals 2007, 2008, 2009, and 2010 denote gate electrodes of the MOS Trs, respectively; 2006 and 2015 indicate back gates; and 2011, 2012, 2013, and 2014 show n.sup.+ regions. In FIG. 2, the n.sup.+ region 2011 becomes a source region of the NMOS Tr M2, the n.sup.+ region 2013 becomes a source region of the NMOS Tr M4, the n.sup.+ region 2012 becomes a drain region of the NMOS Tr M2, and the n.sup.+ region 2014 becomes a drain region of the NMOS Tr M4. The back gate 2006 is set to an n.sup.+ region in order to obtain a potential of the n.sup.- region 2001. The back gate 2015 is set to a p.sup.+ region in order to obtain a potential of the P-type substrate 15.
In the foregoing CMOS inverter, however, when a signal of a micro amplitude is handled, it is important that a threshold level of the CMOS inverter and a DC level of an input signal coincide. In the case where the threshold level of the CMOS inverter is slightly deviated, there is a case where an erroneous operation of the circuit or the like occurs.